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| Z3A43Y680M510KAT2A资料 | |
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Z3A43Y680M510KAT2A PDF Download |
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File Size : 116 KB
Manufacturer:AVX Description:When a logic 0 of TRB is latched in with the falling edge of CE, the ADPCM processor is set to the decoding mode. Data applied at the RSI input is sampled with the falling edge of ASCK into a 5-bit ADPCM serial register. Within the next cycle of CE, the decoder converts the ADPCM input data to an 8-bit companded PCM data after 123 master clocks (CLK). The 8-bit parallel PCM data is loaded into a parallel-to-serial shift register and shifted out at the RSO out- put with the rising edges of PSCK. |
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| 相关型号 | |
| ◆ Z3A43Y680M510KAT2A | |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：Z3A43Y680M510KAT2A 厂 家：AVX 封 装：06+ 批 号：SMD 数 量：120000 说 明：【自己库存】 |
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