 |
|||||||
|
|||||||
|
|
|||||||
|
|||||||
|
|
| UWT1A470MCL1GB资料 | |
|
UWT1A470MCL1GB PDF Download |
|
File Size : 116 KB
Manufacturer:NICHICON Description:LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corre- sponding buffer byte is enabled, and when HIGH, dis- abled. The outputs go to the HIGH Impedance State when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE , forms the device command. See the Command Truth Table item for details on device commands. WE , in conjunction with RAS and CAS , forms the device command. See the Command Truth Table item for details on device commands. VCCQ is the output buffer power supply. VCC is the device internal power supply. GNDQ is the output buffer ground. GND is the device internal ground. |
|
| 相关型号 | |
| ◆ Z3A43Y680M510KAT2A | |
| ◆ Y4C3F104Z500CT | |
| ◆ XCC44N3F470KG1 | |
| ◆ X7R224J5B | |
| ◆ WR06X103JT | |
| ◆ W3L1ZC105MAT1F | |
| ◆ W3A4YG104ZAT1A | |
| ◆ W3A4YC104MAT2A | |
| ◆ W3A45C102MA2TA | |
| ◆ W3A45A470KAT2A | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：UWT1A470MCL1GB 厂 家：NICHICON 封 装：06+ 批 号：SMD 数 量：150000 说 明：【自己库存】 |
|||||
|
运 费： 所在地： 新旧程度： |
|||||
| 联系人：陈生 |
| 电 话：0755-82565235.0755-88391555.0755-82807567 |
| 手 机：13798377798 |
| QQ：819175396,302677436,343000888 |
| MSN：mwdsmd@hotmail.com,xiaowei700@hotmail.com |
| 传 真：0755-83177555 |
| EMail：mwdsmd@126.com |
| 公司地址： 深圳市福田区振中路鼎诚国际1018室 |
