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TN11-3V103JT资料 | |
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TN11-3V103JT PDF Download |
File Size : 116 KB
Manufacturer:MITSUBISHI Description: Typicals represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3VAB = VDD, Wiper (VW) = No connect. 4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6Guaranteed by design and not subject to production test. 7Different from operating power supply, power supply for OTP is used one-time only. 8Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only. 9PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. 10Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value result in the minimum overall power consumption. 11All dynamic characteristics use VDD = 5 V. 12Different from settling time after fuse is blown. The OTP settling time occurs once only. |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:TN11-3V103JT 厂 家:MITSUBISHI 封 装:06+ 批 号:SMD 数 量:320000 说 明:【自己库存】 |
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