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| TN10-2D300JT资料 | |
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TN10-2D300JT PDF Download |
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File Size : 116 KB
Manufacturer:MITSUBISHI Description:Recovery time required when the device goes from power-down mode into bypass mode (test mode with AVDD at GND). ¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TN10-2D300JT 厂 家：MITSUBISHI 封 装：06+ 批 号：SMD 数 量：320000 说 明：【自己库存】 |
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