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| NCP18WB333J03RB资料 | |
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NCP18WB333J03RB PDF Download |
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File Size : 116 KB
Manufacturer:MURATA Description:READ ENABLE ( R ) A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes high, the Data Outputs (Q0 C Q8) will return to a high impedance condition until the next Read operation. When all data has been read from the FIFO, the Empty Flag (EF) will go low, allowing the final read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go high after tWEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes in R will not affect the FIFO when it is empty. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：NCP18WB333J03RB 厂 家：MURATA 封 装：07+ 批 号：SMD 数 量：280000 说 明：【自己库存】 |
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