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| LQP03TN15NJ04D资料 | |
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LQP03TN15NJ04D PDF Download |
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File Size : 116 KB
Manufacturer:MURATA Description:The WRITE instruction is followed by 16 bits of data to be written into the specified address After the last bit of data is put on the data-in (DI) pin CS must be brought low before the next rising edge of the SK clock This falling edge of CS initiates the self-timed programming cycle The DO pin indi- cates the READY BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS) DO e logical 0 indi- cates that programming is still in progress DO e logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruc- tion Erase All (ERAL) The ERAL instruction will simultaneously program all regis- ters in the memory array and set each bit to the logical 1 state The Erase All cycle is identical to the ERASE cycle except for the different op-code As in the ERASE mode the DO pin indicates the READY BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS) The ERASE ALL instruction is not required see note below Write All (WRAL) The WRAL instruction will simultaneously program all regis- ters with the data pattern specified in the instruction As in the WRITE mode the DO pin indicates the READY BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS) Erase Write Disable (EWDS) To protect against accidental data disturb the Erase Write Disable (EWDS) instruction disables all programming modes and should follow all programming operations Execution of a READ instruction is independent of both the EWEN and EWDS instructions |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：LQP03TN15NJ04D 厂 家：MURATA 封 装：06+ 批 号：SMD 数 量：150000 说 明：【自己库存】 |
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