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| GRM39COG7R5D50资料 | |
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GRM39COG7R5D50 PDF Download |
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File Size : 116 KB
Manufacturer:MURATA Description:A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after t PHEL or tPLYH, whichever occurs last. See Table 15 and Figure 12, Reset/Temporary Unprotect AC Char- acteristics for more details. Holding RP at V ID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Reset/Block Temporary Unprotect can be left un- connected. A weak internal pull-up resistor en- sures that the memory always operates correctly. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC4. VSS Ground. The VSS Ground is the reference for all voltage measurements. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：GRM39COG7R5D50 厂 家：MURATA 封 装：06+ 批 号：SMD 数 量：120000 说 明：【自己库存】 |
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运 费： 所在地： 新旧程度： |
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| 联系人：陈生 |
| 电 话：0755-82565235.0755-88391555.0755-82807567 |
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| 公司地址： 深圳市福田区振中路鼎诚国际1018室 |
