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GRM32ER61E226KE15L

GRM32ER61E226KE15L资料
GRM32ER61E226KE15L
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File Size : 116 KB
Manufacturer:MURATA
Description:Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS latches the column addresses. This feature allows the TMS4x100 to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low), if tAA max (access time from column address) has been satisfied. If column addresses for the next cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCAC or tCPA (access time from rising edge of CAS).
 
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型 号:GRM32ER61E226KE15L
厂 家:MURATA
封 装:06+
批 号:SMD
数 量:120000
说 明:【自己库存】
 
 
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