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| GRM2195C1H153JA01D资料 | |
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GRM2195C1H153JA01D PDF Download |
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File Size : 116 KB
Manufacturer:MURATA Description:The CE transmission gate is disabled and CEIN is high impedance (disable mode) while reset is asserted. During a power-down sequence when VDD crosses the reset threshold, the CE transmission gate is disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low when reset is asserted, the CE transmission gate is disabled when CEIN goes high, or 15 µs after reset asserts, whichever occurs first. This allows the current write cycle to complete during power down. When the CE transmission gate is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT. The overall device propagation delay through the CE transmission gate depends on VOUT, the source impedance of the drive connected to CEIN, and the load at CEOUT. To achieve minimum propagation delay, the capacitive load at CEOUT should be minimized, and a low-output-impedance driver is used. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：GRM2195C1H153JA01D 厂 家：MURATA 封 装：06+ 批 号：SMD 数 量：320000 说 明：【自己库存】 |
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运 费： 所在地： 新旧程度： |
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| 联系人：陈生 |
| 电 话：0755-82565235.0755-88391555.0755-82807567 |
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| 公司地址： 深圳市福田区振中路鼎诚国际1018室 |
