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| GRM0334C1E2R0BD01D资料 | |
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GRM0334C1E2R0BD01D PDF Download |
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File Size : 116 KB
Manufacturer:MURATA Description:Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. Eleven row-address bits are set up on inputs A0 through A10 and latched onto the chip by the row-address strobe (RAS). The eleven column-address bits are set up on A0 through A10 and latched onto the chip by the column-address strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffer, as well as latching the address bits into the column-address buffer. |
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| 相关型号 | |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：GRM0334C1E2R0BD01D 厂 家：MURATA 封 装：06+ 批 号：SMD 数 量：120000 说 明：【自己库存】 |
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运 费： 所在地： 新旧程度： |
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| 联系人：陈生 |
| 电 话：0755-82565235.0755-88391555.0755-82807567 |
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| 公司地址： 深圳市福田区振中路鼎诚国际1018室 |
