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| EEUFC1V102B资料 | |
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EEUFC1V102B PDF Download |
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File Size : 116 KB
Manufacturer:Panasonic Description:Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to the embedded clock and uses it to recover the serialized data. ROUTx data is valid when LOCK is low, otherwise ROUT0 C ROUT9 is invalid. The ROUT0CROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be used is selected by the RCLK_R/F input. The ROUT0 C ROUT9, LOCK and RCLK outputs can drive a maximum of three CMOS input gates (15-pF load, total for all three) with a 40-MHz clock. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：EEUFC1V102B 厂 家：Panasonic 封 装：07+ 批 号：DIP 数 量：150000 说 明：【自己库存】 |
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运 费： 所在地： 新旧程度： |
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| 联系人：陈生 |
| 电 话：0755-82565235.0755-88391555.0755-82807567 |
| 手 机：13798377798 |
| QQ：819175396,302677436,343000888 |
| MSN：mwdsmd@hotmail.com,xiaowei700@hotmail.com |
| 传 真：0755-83177555 |
| EMail：mwdsmd@126.com |
| 公司地址： 深圳市福田区振中路鼎诚国际1018室 |
