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| 12065C183KAT2A资料 | |
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12065C183KAT2A PDF Download |
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File Size : 116 KB
Manufacturer:AVX Description:4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space- saving FineLine BGATM , and plastic J-lead chip carrier (PLCC) packages Supports hot-socketing in MAX 7000AE devices Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance PCI-compatible Bus-friendly architecture, including programmable slew-rate control Open-drain output option Programmable macrocell registers with individual clear, preset, clock, and clock enable controls Programmable power-up states for macrocell registers in MAX 7000AE devices Programmable power-saving mode for 50% or greater power reduction in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell Programmable security bit for protection of proprietary designs 6 to 10 pin- or logic-driven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from I/O pin to macrocell registers Programmable output slew-rate control Programmable ground pins |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：12065C183KAT2A 厂 家：AVX 封 装：07+ 批 号：SMD 数 量：480000 说 明：【自己库存】 |
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运 费： 所在地： 新旧程度： |
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