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| 08055A101JAT2A资料 | |
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08055A101JAT2A PDF Download |
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File Size : 116 KB
Manufacturer:AVX Description:The four D-type flip-flops operate synchronously from a com- mon clock. The outputs are in the three-state mode when either of the two output disable pins are at the logic 1 level. The input ENABLES allow the flip-flops to remain in their present states without having to disrupt the clock If either of the 2 input ENABLES are taken to a logic 1 level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Reset is enabled by taking the MASTER RESET (MR) input to a logic 1 level. The data outputs change state on the positive going edge of the clock. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：08055A101JAT2A 厂 家：AVX 封 装：06+ 批 号：SMD 数 量：120000 说 明：【自己库存】 |
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